How to Make a Synthetic Multicellular Computer
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{"title"=>"How to make a synthetic multicellular computer", "type"=>"journal", "authors"=>[{"first_name"=>"Javier", "last_name"=>"Macia", "scopus_author_id"=>"56259689100"}, {"first_name"=>"Ricard", "last_name"=>"Sole", "scopus_author_id"=>"7004381560"}], "year"=>2014, "source"=>"PLoS ONE", "identifiers"=>{"scopus"=>"2-s2.0-84897753448", "pmid"=>"24586222", "sgr"=>"84897753448", "doi"=>"10.1371/journal.pone.0081248", "isbn"=>"1932-6203 (Electronic)\\r1932-6203 (Linking)", "issn"=>"19326203", "pui"=>"372566154"}, "id"=>"94b605e4-98d1-3799-87b3-9f5e55694f79", "abstract"=>"Biological systems perform computations at multiple scales and they do so in a robust way. Engineering metaphors have often been used in order to provide a rationale for modeling cellular and molecular computing networks and as the basis for their synthetic design. However, a major constraint in this mapping between electronic and wet computational circuits is the wiring problem. Although wires are identical within electronic devices, they must be different when using synthetic biology designs. Moreover, in most cases the designed molecular systems cannot be reused for other functions. A new approximation allows us to simplify the problem by using synthetic cellular consortia where the output of the computation is distributed over multiple engineered cells. By evolving circuits in silico, we can obtain the minimal sets of Boolean units required to solve the given problem at the lowest cost using cellular consortia. Our analysis reveals that the basic set of logic units is typically non-standard. Among the most common units, the so called inverted IMPLIES (N-Implies) appears to be one of the most important elements along with the NOT and AND functions. Although NOR and NAND gates are widely used in electronics, evolved circuits based on combinations of these gates are rare, thus suggesting that the strategy of combining the same basic logic gates might be inappropriate in order to easily implement synthetic computational constructs. The implications for future synthetic designs, the general view of synthetic biology as a standard engineering domain, as well as potencial drawbacks are outlined.", "link"=>"http://www.mendeley.com/research/make-synthetic-multicellular-computer", "reader_count"=>87, "reader_count_by_academic_status"=>{"Unspecified"=>1, "Professor > Associate Professor"=>4, "Librarian"=>1, "Researcher"=>16, "Student > Doctoral Student"=>4, "Student > Ph. D. Student"=>29, "Student > Postgraduate"=>2, "Student > Master"=>13, "Other"=>3, "Student > Bachelor"=>10, "Lecturer > Senior Lecturer"=>1, "Professor"=>3}, "reader_count_by_user_role"=>{"Unspecified"=>1, "Professor > Associate Professor"=>4, "Librarian"=>1, "Researcher"=>16, "Student > Doctoral Student"=>4, "Student > Ph. D. Student"=>29, "Student > Postgraduate"=>2, "Student > Master"=>13, "Other"=>3, "Student > Bachelor"=>10, "Lecturer > Senior Lecturer"=>1, "Professor"=>3}, "reader_count_by_subject_area"=>{"Engineering"=>16, "Unspecified"=>2, "Environmental Science"=>1, "Biochemistry, Genetics and Molecular Biology"=>14, "Agricultural and Biological Sciences"=>33, "Chemical Engineering"=>1, "Physics and Astronomy"=>4, "Chemistry"=>3, "Social Sciences"=>2, "Computer Science"=>8, "Immunology and Microbiology"=>2, "Earth and Planetary Sciences"=>1}, "reader_count_by_subdiscipline"=>{"Engineering"=>{"Engineering"=>16}, "Chemistry"=>{"Chemistry"=>3}, "Social Sciences"=>{"Social Sciences"=>2}, "Physics and Astronomy"=>{"Physics and Astronomy"=>4}, "Immunology and Microbiology"=>{"Immunology and Microbiology"=>2}, "Earth and Planetary Sciences"=>{"Earth and Planetary Sciences"=>1}, "Agricultural and Biological Sciences"=>{"Agricultural and Biological Sciences"=>33}, "Computer Science"=>{"Computer Science"=>8}, "Biochemistry, Genetics and Molecular Biology"=>{"Biochemistry, Genetics and Molecular Biology"=>14}, "Unspecified"=>{"Unspecified"=>2}, "Environmental Science"=>{"Environmental Science"=>1}, "Chemical Engineering"=>{"Chemical Engineering"=>1}}, "reader_count_by_country"=>{"Vietnam"=>1, "Luxembourg"=>1, "China"=>1, "United Kingdom"=>2, "Mexico"=>1, "France"=>1, "Portugal"=>1, "Spain"=>5}, "group_count"=>2}

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Figshare

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  • {"files"=>["https://ndownloader.figshare.com/files/1391699"], "description"=>"<p>Truth table for a Boolean function.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "boolean"], "article_id"=>939079, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.t001", "stats"=>{"downloads"=>0, "page_views"=>0, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Truth_table_for_a_Boolean_function_/939079", "title"=>"Truth table for a Boolean function.", "pos_in_sequence"=>0, "defined_type"=>3, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391700"], "description"=>"<p>Truth table for a 3-Parity bit circuit.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "3-parity"], "article_id"=>939080, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.t005", "stats"=>{"downloads"=>4, "page_views"=>11, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Truth_table_for_a_3_Parity_bit_circuit_/939080", "title"=>"Truth table for a 3-Parity bit circuit.", "pos_in_sequence"=>0, "defined_type"=>3, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391698"], "description"=>"<p>Truth table for a Boolean function.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "boolean"], "article_id"=>939078, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.t002", "stats"=>{"downloads"=>1, "page_views"=>3, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Truth_table_for_a_Boolean_function_/939078", "title"=>"Truth table for a Boolean function.", "pos_in_sequence"=>0, "defined_type"=>3, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391679"], "description"=>"<p>Combinatorial circuits are constructed in conventional electronic design by using predefined gates and wiring them in order to execute a given input-output table. This is illustrated by the so called multiplexer (MUX) circuit, whose representation and logic table is shown in (a). Using AND and NOT gates, a standard implementation is displayed in (b). In (c) we show an example of a synthetic gene network implementing a single-cell multiplexer. The output signal is a GFP reporter. A very different design of the MUX system is shown in (d). Here the circuit can be easily designed by splitting the computation into two separated <i>and disconnected</i> engineered cells, both able to display the output signal. A simplified diagram that summarized the logic of (d) is shown in (e).</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "non-standard", "circuit"], "article_id"=>939060, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.g002", "stats"=>{"downloads"=>0, "page_views"=>1, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Standard_and_non_standard_circuit_design_/939060", "title"=>"Standard and non-standard circuit design.", "pos_in_sequence"=>0, "defined_type"=>1, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391676"], "description"=>"<p>The NAND gate (a) is obtained as a sequential combination of AND and NOT gates. The compressed symbol is shown in (b) along with the truth table. An example of a synthetic implementation of the NAND logic can be made (c) using genetic regulatory elements A and B forming a regulatory heterodimer complex that prevents the expression of the reporter gene. In conventional electronics, combinations of such gates allow to construct more complex circuits and chips (d), which are then used as basic modules for further circuit designs.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "gates", "implemented", "sets"], "article_id"=>939056, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.g001", "stats"=>{"downloads"=>0, "page_views"=>1, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Simple_logic_gates_can_be_implemented_out_from_minimal_sets_of_logic_units_/939056", "title"=>"Simple logic gates can be implemented out from minimal sets of logic units.", "pos_in_sequence"=>0, "defined_type"=>1, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391689"], "description"=>"<p>In (a) we consider a complex, nontrivial 4-input 1-output Boolean function analysed in Marchisio and Stelling 2011 <a href=\"http://www.plosone.org/article/info:doi/10.1371/journal.pone.0081248#pone.0081248-Marchisio2\" target=\"_blank\">[57]</a>. Figure shows the truth table and the standard design using two-input gates along with NOT gates. Below (b) we display a minimal circuit implementing this function. In (c) a two-bits comparator circuit is implemented according with the standard methodology, whereas in (d) an alternative design obtained by evolution is shown involving less gates an wires Only two communication signals (wires) are required for this implementation. Two colours (red and yellow) are used to indicate the two reporter molecules associated to each possible output (either or ).</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering"], "article_id"=>939069, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.g006", "stats"=>{"downloads"=>0, "page_views"=>3, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Scaling_up_DMC_/939069", "title"=>"Scaling up DMC.", "pos_in_sequence"=>0, "defined_type"=>1, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391685"], "description"=>"<p>The coloured balls represent the basic set of engineered cells indicating their internal Boolean functions. The dashed boxes indicate subsets of cells linked through the same communication signal (wire) represented by coloured dashed arrows. In (a) the binary comparator circuit is shown, after all simplifications have been performed. Figure (b) shows a DMC circuit implementing a binary three-bits adder using distributed logic. Finally, in (c) we display the minimal three-bit parity circuit is shown. Although the standard circuit is quite complex, a cell consortia involving six different cell types is enough to implement this complex function. Of note, these examples involve two different wires at the most in the most complex circuit and hence a real wet lab implementation is feasible.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "dmc", "designs", "evolutionary", "algorithm", "solutions", "computational", "defined", "boolean", "tables", "examples"], "article_id"=>939065, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.g005", "stats"=>{"downloads"=>1, "page_views"=>20, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Examples_DMC_designs_obtained_by_using_an_evolutionary_algorithm_to_find_solutions_to_given_computational_functions_as_defined_by_Boolean_tables_of_the_examples_shown_in_figure_4_/939065", "title"=>"Examples DMC designs obtained by using an evolutionary algorithm to find solutions to given computational functions, as defined by Boolean tables of the examples shown in figure 4.", "pos_in_sequence"=>0, "defined_type"=>1, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391684"], "description"=>"<p>(a) Two-bit comparator (b) the three-bit adder and (c) a 3-bit parity circuit. Here the set of inputs appears indicated as open squares and the single-output element is marked as GFP. The left and right columns are different implementations of the same circuits design (Boolean table) but they have been constructed used diverse logic gates (left) or only using NAND gates with variable numbers of inputs. These circuits have been generated using the <i>Logisim</i> software package. Once the truth table is provided, it builds the logic circuits, either choosing the appropriate set of two-input logic gates or using just NAND gates. If the NAND gates were chosen such that they only include two inputs, the circuits would be much more complex.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "designs", "cases"], "article_id"=>939064, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.g004", "stats"=>{"downloads"=>1, "page_views"=>11, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Examples_of_standard_engineering_designs_of_three_cases_studies_/939064", "title"=>"Examples of standard engineering designs of three cases studies.", "pos_in_sequence"=>0, "defined_type"=>1, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391697"], "description"=>"<p>Truth table for a Two-bits magnitude comparator.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "two-bits"], "article_id"=>939077, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.t003", "stats"=>{"downloads"=>0, "page_views"=>10, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Truth_table_for_a_Two_bits_magnitude_comparator_/939077", "title"=>"Truth table for a Two-bits magnitude comparator.", "pos_in_sequence"=>0, "defined_type"=>3, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391682"], "description"=>"<p>Here each engineered cell is indicated as and wires generated by are indicated as . Cell will produce an output according with the logic defined by . Here represents the <i>k</i>-th logic gate responding to two inputs, the external one and the internal wire secreted by cell . The upper layer involves single-input gates, i.e. (thus only the identity or NOT are possible). Different motifs of connections can emerge according with the criteria introduced, such as independent strings of connected cells, where each cell responds to different wire (a), the same wire can be sensed by more than one cell (b), or a given cell responds to wires produced in more than one cell (c). In this last case, due to cells only can sense two inputs (one external and one internal) all wires produced in different parts of the circuit but sensed by the same cell must be implemented using the same diffusible molecule, i.e. wire and are implemented by the same molecule, which can be produced in cells and independently. This situation corresponds to an implicit implementation in of the OR logic with respect to wires and . Yellow cells (, , and ) can produce independently the final output signal e.g. a GFP.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "circuit", "multicellular"], "article_id"=>939062, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.g003", "stats"=>{"downloads"=>0, "page_views"=>1, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_A_general_circuit_design_can_be_obtained_by_starting_from_a_multicellular_system_where_each_virtual_cell_is_a_given_logic_gate_/939062", "title"=>"A general circuit design can be obtained by starting from a multicellular system where each virtual cell is a given logic gate.", "pos_in_sequence"=>0, "defined_type"=>1, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391696"], "description"=>"<p>In (a) the graph displays the frequency of appearance of different logic gates for circuits evolved without any specific evolutionary pressure (red), imposing minimum size (green), and under minimal circuits complexity (blue). These frequencies have been calculated as the average results for runs. In (b) the graph displays the average results for runs of an evolutionary pressure towards minimum size. The frequency of a given gate is proportional to node diameter, whereas the probability of finding two gates in the same circuit is given by the link weights. In (c) we show the corresponding results for evolved networks under minimal circuits complexity. In both cases, the most represented gates are NOT, AND, , and NOR.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "gates", "circuits", "evolved", "evolutionary"], "article_id"=>939076, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.g008", "stats"=>{"downloads"=>0, "page_views"=>6, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Frequency_of_appearance_of_different_logic_gates_for_circuits_evolved_without_evolutionary_pressure_/939076", "title"=>"Frequency of appearance of different logic gates for circuits evolved without evolutionary pressure.", "pos_in_sequence"=>0, "defined_type"=>1, "published_date"=>"2014-02-19 03:27:47"}
  • {"files"=>["https://ndownloader.figshare.com/files/1391691"], "description"=>"<p>(a) Weighted graph showing the frequency of gates used in the generation of evolved MUX circuits under DMC. The diameter of the nodes is proportional to the frequency of the gate. Links indicate that two gates have been wired together within a circuit. The weights provide a measure of how frequently a given pair has been used. Note the disproportionate frequency of N-implies () which are typically connected to NOT and AND gates, much less with NOR gates. Note also the vanishing frequency of NOR-NOR links (see text). In (b) we summarize the relative frequencies of different gates. The two N-Implies gates (here NI = N1+IN2) have been added together. These and the NOR abundances are highlighted with distinctive colours. Circuits were evolved imposing minimal number of wires.</p>", "links"=>[], "tags"=>["biotechnology", "Bioengineering", "Biomedical Engineering", "Computational biology", "Synthetic Biology", "Computer architecture", "Computerized simulations", "Electrical engineering", "Computer engineering", "gates", "mux"], "article_id"=>939071, "categories"=>["Biological Sciences", "Engineering"], "users"=>["Javier Macía", "Ricard Solé"], "doi"=>"https://dx.doi.org/10.1371/journal.pone.0081248.g007", "stats"=>{"downloads"=>0, "page_views"=>3, "likes"=>0}, "figshare_url"=>"https://figshare.com/articles/_Graphs_showing_the_frequency_of_gates_in_a_MUX_circuit_/939071", "title"=>"Graphs showing the frequency of gates in a MUX circuit.", "pos_in_sequence"=>0, "defined_type"=>1, "published_date"=>"2014-02-19 03:27:47"}

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